Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation. One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
An integrated circuit, such as an FPGA, may include one or more interfaces for communicating information. There are many known types of interfaces, such as a Peripheral Component Interconnect (“PCI”), a Universal Serial Bus (“USB”), and Ethernet, among other known interfaces. For purposes of clarity, by way of example it shall be assumed that a PCI Express (“PCIe”) interface is used for an integrated circuit, although it shall be appreciated from the following description that other types of known interfaces may be used.
For operation of a PCIe interface, a user clock and a core clock are supplied. Conventionally, the user clock and the core clock are synchronous with respect to one another and are edge-aligned with some uncertainty. For example, the user clock may be rising edge-aligned to rising edges of the core clock with some uncertainty. Furthermore, for a PCI, the core clock signal is provided at a standard specified frequency, which for a PCIe is presently approximately 250 MHz. However, uncertainty with respect to such edge alignment translates into having to have larger timing margins. In short, this means that the “windows of operation” have to be increased to accommodate such uncertainty, which generally slows performance.
Accordingly, it would be desirable and useful to provide a dual clock interface that at least reduces the above-described uncertainty such that performance may be enhanced with narrower timing margins.